I defended my thesis on 15 February 2006. I'll eventually write up a more thorough summary, but briefly I designed and tested two analog VLSI chips, one of which made it into my thesis. The most interesting part of the first chip (not in the thesis) was an analog multiplier, similar to a Gilbert multiplier, with floating gates (EEPROM) embedded and programmable to remove mismatch from the circuit. The second chip incorporated an array of local image processing elements, each containing a photodiode and some analog circuitry. Floating gates within the pixels and a novel analog difference circuit can be programmed to reduce mismatch. The chip could be used as a front-end feature detector coupled with a digital post-processor (ex. an FPGA) to solve a task such as self-motion estimation.

You can download my thesis in PDF.